Four-phase charge pump circuit

ABSTRACT

A four-phase charge pump circuit including an output stage and multiple boosting stages is provided. The multiple boosting stages are coupled to the output stage in series, and each of the multiple boosting stages is driven by four-phase clock signals. The output stage is driven by two clock signals of the four-phase clock signals and outputs a positive boosted voltage, and thereby the four-phase charge pump circuit is a positive charge pump circuit. Each of the boosting stages includes two branch charge pumps, and each of the two branch charge pumps includes a main pass transistor and a pre-charge transistor. The main pass transistors and the pre-charge transistors of the boosting stages are disposed on an identical deep doped region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefits of U.S. provisionalapplication Ser. No. 62/021,216, filed on Jul. 7, 2014. The entirety ofthe above-mentioned patent application is hereby incorporated byreference herein and made a part of this specification.

BACKGROUND

1. Technical Field

The disclosure relates to a charge pump circuit. Particularly, thedisclosure relates to a four-phase charge pump circuit.

2. Related Art

In order to lower power consumption, an operating voltage for integratedcircuits (ICs) is modified to a lower level. For example, the normaloperating voltage for the ICs has been changed from the early 5 volts tothe present 3.3 volts, and sometimes even lower than 2 volts. Although alower operating voltage is beneficial for power consumption reduction,some particular applications requiring a high operating voltage stillshould be concerned. In particular, while erasing data stored in a flashmemory, a high voltage, is necessary and supplied by a charge pumpcircuit.

Generally, a charge pump circuit supplying positive voltage is composedof P-channel metal-oxide-semiconductor (PMOS) transistors. On thecontrary, a charge pump circuit supplying negative voltage could becomposed of NMOS transistors. However, PMOS transistors have weakerdriving capability and lower transconductance than NMOS transistors suchthat a PMOS type charge pump circuit is less efficient or occupiesrelatively larger area than a NMOS type charge pump circuit in certainoperation conditions.

SUMMARY

The disclosure is directed to a four-phase charge pump circuit, whichoccupies relatively small chip area.

The disclosure provides a four-phase charge pump circuit includingmultiple boosting stages. The boosting stages are driven by four-phaseclock signals. Each of the boosting stages includes two branch chargepumps, and each of the two branch charge pumps includes a main passtransistor and a pre-charge transistor. The main pass transistor has abody, a gate terminal, a source terminal as a first node of the branchcharge pump and a drain terminal as a second node of the branch chargepump. The first node and the second node of the branch charge pumpconnect respectively to a front boosting stage and a rear boosting stageof the boosting stages. The pre-charge transistor has a gate terminal, asource terminal and a drain terminal. The source terminal and the drainterminal of the pre-charge transistor are respectively coupled to thegate terminal of the main transistor and the first node of the branchcharge pump. The gate terminal of the pre-charge transistor is coupledto the second node of the branch charge pump. The main pass transistorsand the pre-charge transistors of the boosting stages are disposed on anidentical deep doped region.

In an embodiment of the disclosure, each of the two branch charge pumpsfurther includes two capacitors. The two capacitors are coupledrespectively to the gate terminal of the main pass transistor and thesecond node of the branch charge pump.

In an embodiment of the disclosure, for each of the boosting stages, thetwo capacitors of one branch charge pump receive two clock signals ofthe four-phase clock signals, and the two capacitors of the other branchcharge pump receive the other two clock signals of the four-phase clocksignals.

In an embodiment of the disclosure, each of the two branch charge pumpsfurther includes two substrate transistors. Each of the two substratetransistors has a body, a gate terminal, a source terminal and a drainterminal. The source terminals and the bodies of the two substratetransistors are connected together to the body of the main passtransistor. The drain terminals of the two substrate transistors areconnected respectively to the first node and the second node of thebranch charge pump. The gate terminal of one substrate transistor, whosedrain terminal connects to the second node, is connected to the firstnode of one branch charge pump that the one substrate transistor islocated, and the gate terminal of the other substrate transistor isconnected to the first node of the other branch charge pump.

In an embodiment of the disclosure, each of the two branch charge pumpsfurther includes an initial transistor. The initial transistor has abody, a gate terminal, a source terminal and a drain terminal. The drainterminal and the source terminal of the initial transistor arerespectively coupled to the first node and the second node of the branchcharge pump. The gate terminal of the initial transistor is coupled tothe drain terminal of the initial transistor, and the body of theinitial transistor are connected to the body of the main passtransistor.

In an embodiment of the disclosure, potential at the body of each of themain pass transistors and the initial transistors of the boosting stagesis kept at a lower substrate level.

In an embodiment of the disclosure, the substrate transistors and theinitial transistors of the boosting stages are disposed on the identicaldeep doped region.

In an embodiment of the disclosure, the main pass transistors, thepre-charge transistors, the substrate transistors and the initialtransistors of the boosting stages are N-channelmetal-oxide-semiconductor field-effect transistors (MOSFETs).

In an embodiment of the disclosure, the four-phase charge pump circuitfurther includes an output stage. The output stage is driven by twoclock signals of the four-phase clock signals and outputs a boostedvoltage. The multiple boosting stages are coupled to the output stage.

In an embodiment of the disclosure, the output stage includes two branchoutput circuits, and each of the two branch output circuits includes amain pass transistor and a pre-charge transistor. The main passtransistor has a body, a gate terminal, a source terminal as a firstnode of the branch output circuit and a drain terminal as a second nodeof the branch output circuit. The first node of the branch outputcircuit connects to a front boosting stage of the boosting stages, andthe second node of the branch output circuit serves as an output end ofthe output stage to output the boosted voltage. The pre-chargetransistor has a gate terminal, a source terminal and a drain terminal.The source terminal and the drain terminal of the pre-charge transistorare respectively coupled to the gate terminal of the main transistor andthe first node of the branch output circuit, and the gate terminal ofthe pre-charge transistor is coupled to the second node of the branchoutput circuit. The main pass transistors and the pre-charge transistorsof the output stage are disposed on the identical deep doped region.

In an embodiment of the disclosure, each of the two branch outputcircuits further includes one capacitor. The one capacitor is coupled tothe gate terminal of the main pass transistor. The capacitors of theoutput stage receive two clock signals of the four-phase clock signals.

In an embodiment of the disclosure, each of the two branch charge pumpsfurther includes two substrate transistors. Each of The two substratetransistors has a body, a gate terminal, a source terminal and a drainterminal. The source terminals and the bodies of the two substratetransistors are connected together to the body of the main passtransistor. The drain terminals of the two substrate transistors areconnected respectively to the first node and the second node of thebranch output circuit. The gate terminal of one substrate transistor,whose drain terminal connects to the second node, is connected to thefirst node of one branch output circuit that the one substratetransistor is located, and the gate terminal of the other substratetransistor is connected to the first node of the other branch outputcircuit.

In an embodiment of the disclosure, potential at the body of each of themain pass transistors of the output stage is kept at a lower substratelevel.

In an embodiment of the disclosure, the substrate transistors of theoutput stage are disposed on the identical deep doped region.

In an embodiment of the disclosure, the main pass transistors, thepre-charge transistors and the substrate transistors of the output stageare N-channel MOSFETs.

In an embodiment of the disclosure, the four-phase charge pump circuitis a positive charge pump circuit.

According to the above descriptions, the transistors of the multipleboosting stages in the disclosure are disposed on the same deep dopedregion, and thereby the occupied chip area may be reduced and smallerthan that of the charge pump circuit whose deep doped region areseparated for each boosting stage.

In order to make the aforementioned and other features and advantages ofthe disclosure comprehensible, several exemplary embodiments accompaniedwith figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the disclosure, and are incorporated in and constitutea part of this specification. The drawings illustrate embodiments of thedisclosure and, together with the description, serve to explain theprinciples of the disclosure.

FIG. 1 is a schematic diagram of a four-phase charge pump circuitaccording to an embodiment of the disclosure.

FIG. 2A shows waveforms of four-phase clock signals applied for thecircuit of FIG. 1 in accordance with an embodiment of the disclosure.

FIG. 2B shows waveforms of four-phase clock signals applied for thecircuit of FIG. 1 in accordance with another embodiment of thedisclosure.

FIG. 3 illustrates an internal circuit structure of the odd-numberedvoltage boosting stage according to the embodiment of FIG. 1.

FIG. 4 illustrates an internal circuit structure of the even-numberedvoltage boosting stage according to the embodiment of FIG. 1.

FIG. 5 illustrates an internal circuit structure of the output stageaccording to the embodiment of FIG. 1.

FIG. 6 illustrates a schematic structure drawing of the multipleboosting stages according to an exemplary embodiment of the disclosure.

FIG. 7 illustrates a schematic circuit diagram of each transistor of theboosting stages.

FIG. 8 is a schematic diagram of a four-phase charge pump circuitaccording to another embodiment of the disclosure.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

The term “coupling/coupled” used in this specification (includingclaims) may refer to any direct or indirect connection means. Forexample, “a first device is coupled to a second device” should beinterpreted as “the first device is directly connected to the seconddevice” or “the first device is indirectly connected to the seconddevice through other devices or connection means.” Moreover, whereverappropriate in the drawings and embodiments, elements/components/stepswith the same reference numerals represent the same or similar parts.Elements/components/steps with the same reference numerals or names indifferent embodiments may be cross-referenced. A plurality ofembodiments are provided below to describe the disclosure in detail,though the disclosure is not limited to the provided embodiments, andthe provided embodiments can be suitably combined.

FIG. 1 is a schematic diagram of a four-phase charge pump circuitaccording to an embodiment of the disclosure. FIG. 2A shows waveforms offour-phase clock signals applied for the circuit of FIG. 1 in accordancewith an embodiment of the disclosure. With reference to FIG. 1 and FIG.2A, a four-phase charge pump circuit 100 in accordance with thedisclosure includes an output stage 110 and multiple boosting stages120_1 to 120_N, where N is a positive integer larger than 1. Themultiple boosting stages 120_1 to 120_N are coupled to the output stage110 in series, and each of the multiple boosting stages 120_1 to 120_Nis driven by the four-phase clock signals P11, P22, P33 and P44 as shownin FIG. 2A. The output stage 110 is driven by the four-phase clocksignals P22 and P44 and outputs a positive boosted voltage VPP, andthereby the four-phase charge pump circuit 100 is a positive charge pumpcircuit.

In the embodiment as exemplarily disclosed in FIG. 1, the four-phasecharge pump circuit 100 may include even-numbered boosting stages 120_1to 120_N, i.e., N is an even number larger than 1. The boosting stage120_1 receives an input voltage VDD, and the input voltage VDD issequentially boosted by the multiple boosting stages 120_1 to 120_Nstage by stage, and then the boosting stage 120_N outputs middle boostedvoltages UN and DN to the output stage 110. In this case, the middleboosted voltages UN and DN outputted to the output stage 110 may be N+1times larger than the input voltage VDD, e.g., UN=(N+1) VDD. The outputstage 110 receives the middle boosted voltages UN and DN and enhancesthe driving capability of the middle boosted voltages UN and DN tothereby generate the positive boosted voltage VPP.

It should be noted that, an amount of the multiple boosting stages 120_1to 120_N included in the four-phase charge pump circuit 100 in thepresent embodiment may be adjusted according to different actual circuitdesign, which are not particularly limited by the disclosure. In otherexemplary embodiments, the four-phase charge pump circuit 100 mayinclude odd-numbered boosting stages 120_1 to 120_N, i.e., N is an oddnumber larger than 1. In this case, the output stage 110 may be drivenin another manner. The upper branch output circuit inside the outputstage 110 may be driven by the clock signal P22, and the lower branchoutput circuit inside the output stage 110 may be driven by the clocksignal P44.

FIG. 3 illustrates an internal circuit structure of the odd-numberedvoltage boosting stage according to the embodiment of FIG. 1. Referringto FIG. 3, the internal circuit structure of the voltage boosting stage120_1, 120_3 . . . or 120_(N−1) (not shown in FIG. 1) is illustrated inFIG. 3. The voltage boosting stage 120_1 is taken as an example in thefollowing description, and the other voltage boosting stage 120_3 . . .and 120_(N−1) can be deduced by analogy.

In the present embodiment, the voltage boosting stage 120_1 includes anupper branch charge pump 121 and a lower branch charge pump 123. Theupper branch charge pump 121 includes a main pass transistor NO, apre-charge transistor N3, two capacitors C1 and C2, two substratetransistors N1 and N2 and an initial transistor N6. The source terminalof the main pass transistor NO serves as a first node U0 of the upperbranch charge pump 121, and the drain terminal of the main passtransistor N0 serves as a second node U1 of the upper branch charge pump121. In this embodiment, the voltage boosting stage 120_1 is the firstvoltage boosting stage of the boosting stages 120_1 to 120_N and therebyconfigured to receive the input voltage VDD via the input pads IN1 andIN2. The first node U0 of the upper branch charge pump 121 receives theinput voltage VDD via the input pad IN1. The second node U1 of the upperbranch charge pump 121 connect to the rear boosting stage 120_2 via theoutput pad OUT1. The source terminal and the drain terminal of thepre-charge transistor N3 are respectively coupled to the gate terminalof the main transistor NO and the first node U0 of the upper branchcharge pump 121, and the gate terminal of the pre-charge transistor N3is coupled to the second node U1 of the upper branch charge pump 121.The body of the pre-charge transistor N3 are connected to the body BU ofthe main pass transistor NO. One terminal of the capacitor C2 is coupledto the gate terminal of the main pass transistor NO, and the otherterminal of the capacitor C2 receives the clock signal P44. One terminalof the capacitor C1 is coupled to the second node U1 of the upper branchcharge pump 121, and the other terminal of the capacitor C1 receives theclock signal P11. The source terminals and the bodies of the twosubstrate transistors N1 and N2 are connected together to the body BU ofthe main pass transistor NO, and the drain terminals of the twosubstrate transistors N1 and N2 are connected respectively to the firstnode U0 and the second node U1 of the upper branch charge pump 121. Thegate terminal of the substrate transistor N2 is connected to the firstnode U0 of the upper branch charge pump 121, and the gate terminal ofthe substrate transistor N1 is connected to the first node D0 of thelower branch charge pump 123. That is to say, in the upper branch chargepump 121 of the present embodiment, the gate terminal of one substratetransistor N2, whose drain terminal connects to the second node U1, isconnected to the first node U0 of one branch charge pump 121 that theone substrate transistor N2 is located, and the gate terminal of theother substrate transistor N1 is connected to the first node D0 of theother branch charge pump 123. The substrate transistors N1 and N2 areswitched to keep potential at the body BU of the main pass transistor N0at a lower substrate level to mitigate the body effect. The drainterminal and the source terminal of the initial transistor N6 arerespectively coupled to the first node and the second node of the upperbranch charge pump 121, i.e., the input pad IN1 and the output pad OUT1.The gate terminal of the initial transistor N6 is coupled to the drainterminal itself, and the body of the initial transistor N6 are connectedto the body BU of the main pass transistor N0.

Similarly, the lower branch charge pump 123 also includes a main passtransistor N7, a pre-charge transistor N10, two capacitors C3 and C4,two substrate transistors N8 and N9 and an initial transistor N13. Thesource terminal of the main pass transistor N7 serves as a first node D0of the lower branch charge pump 123, and the drain terminal of the mainpass transistor N7 serves as a second node D1 of the lower branch chargepump 123. In this embodiment, the first node D0 of the lower branchcharge pump 123 receives the input voltage VDD via the input pad IN2.The second node D1 of the lower branch charge pump 123 connect to therear boosting stage 120_2 via the output pad OUT2. The source terminaland the drain terminal of the pre-charge transistor N10 are respectivelycoupled to the gate terminal of the main transistor N7 and the firstnode D0 of the lower branch charge pump 123, and the gate terminal ofthe pre-charge transistor N10 is coupled to the second node D1 of thelower branch charge pump 123. The body of the pre-charge transistor N10are connected to the body BD of the main pass transistor N7. Oneterminal of the capacitor C4 is coupled to the gate terminal of the mainpass transistor N7, and the other terminal of the capacitor C4 receivesthe clock signal P22. One terminal of the capacitor C3 is coupled to thesecond node D1 of the lower branch charge pump 123, and the otherterminal of the capacitor C3 receives the clock signal P33. The sourceterminals and the bodies of the two substrate transistors N8 and N9 areconnected together to the body BD of the main pass transistor N7, andthe drain terminals of the two substrate transistors N8 and N9 areconnected respectively to the first node D0 and the second node D1 ofthe lower branch charge pump 123. The gate terminal of the substratetransistor N9 is connected to the first node D0 of the lower branchcharge pump 123, and the gate terminal of the substrate transistor N8 isconnected to the first node U0 of the upper branch charge pump 121. Thatis to say, in the lower branch charge pump 123 of the presentembodiment, the gate terminal of one substrate transistor N9, whosedrain terminal connects to the second node D1, is connected to the firstnode D0 of one branch charge pump 123 that the one substrate transistorN9 is located, and the gate terminal of the other substrate transistorN8 is connected to the first node U0 of the other branch charge pump121. The substrate transistors N8 and N9 are switched to keep potentialat the body BD of the main pass transistor N7 at a lower substrate levelto mitigate the body effect. The drain terminal and the source terminalof the initial transistor N13 are respectively coupled to the first nodeand the second node of the lower branch charge pump 123, i.e., the inputpad IN2 and the output pad OUT2. The gate terminal of the initialtransistor N13 is coupled to the drain terminal itself, and the body ofthe initial transistor N13 are connected to the body BD of the main passtransistor N7.

FIG. 4 illustrates an internal circuit structure of the even-numberedvoltage boosting stage according to the embodiment of FIG. 1. Referringto FIG. 4, the internal circuit structure of the voltage boosting stage120_2, 120_4 (not shown in FIG. 1) . . . or 120_N is illustrated in FIG.4. The voltage boosting stage 120_2 is taken as an example in thefollowing description, and the other voltage boosting stage 120_4 . . .and 120_N can be deduced by analogy.

In the present embodiment, the voltage boosting stage 120_2 includes anupper branch charge pump 122 and a lower branch charge pump 124. Theupper branch charge pump 122 includes a main pass transistor NO, apre-charge transistor N3, two capacitors C1 and C2, two substratetransistors N1 and N2 and an initial transistor N6. The source terminalof the main pass transistor NO serves as a first node U1 of the upperbranch charge pump 122, and the drain terminal of the main passtransistor NO serves as a second node U2 of the upper branch charge pump122. In this embodiment, the first node U1 of the upper branch chargepump 122 connect to the front boosting stage 120_1 via the input padIN1. The second node U2 of the upper branch charge pump 122 connect tothe rear boosting stage 120_3 via the output pad OUT1. In FIG. 1, thevoltage boosting stage 120_N is the last voltage boosting stage of theboosting stages 120_1 to 120_N and thereby configured to respectivelyoutput the middle boosted voltages UN and DN via the output pads OUT1and OUT2. The source terminal and the drain terminal of the pre-chargetransistor N3 are respectively coupled to the gate terminal of the maintransistor NO and the first node U1 of the upper branch charge pump 122,and the gate terminal of the pre-charge transistor N3 is coupled to thesecond node U2 of the upper branch charge pump 122. The body of thepre-charge transistor N3 are connected to the body BU of the main passtransistor N0. One terminal of the capacitor C2 is coupled to the gateterminal of the main pass transistor N0, and the other terminal of thecapacitor C2 receives the clock signal P22. One terminal of thecapacitor C1 is coupled to the second node U2 of the upper branch chargepump 122, and the other terminal of the capacitor C1 receives the clocksignal P33. The source terminals and the bodies of the two substratetransistors N1 and N2 are connected together to the body BU of the mainpass transistor NO, and the drain terminals of the two substratetransistors N1 and N2 are connected respectively to the first node U1and the second node U2 of the upper branch charge pump 122. The gateterminal of the substrate transistor N2 is connected to the first nodeU1 of the upper branch charge pump 122, and the gate terminal of thesubstrate transistor N1 is connected to the first node D1 of the lowerbranch charge pump 124. That is to say, in the upper branch charge pump122 of the present embodiment, the gate terminal of one substratetransistor N2, whose drain terminal connects to the second node U2, isconnected to the first node U1 of one branch charge pump 122 that theone substrate transistor N2 is located, and the gate terminal of theother substrate transistor N1 is connected to the first node D1 of theother branch charge pump 124. The substrate transistors N1 and N2 areswitched to keep potential at the body BU of the main pass transistor NOat a lower substrate level to mitigate the body effect. The drainterminal and the source terminal of the initial transistor N6 arerespectively coupled to the first node and the second node, i.e., theinput pad IN1 and the output pad OUT1. The gate terminal of the initialtransistor N6 is coupled to the drain terminal itself, and the body ofthe initial transistor N6 are connected to the body BU of the main passtransistor NO.

Similarly, the lower branch charge pump 124 also includes a main passtransistor N7, a pre-charge transistor N10, two capacitors C3 and C4,two substrate transistors N8 and N9 and an initial transistor N13. Thesource terminal of the main pass transistor N7 serves as a first node D1of the lower branch charge pump 124, and the drain terminal of the mainpass transistor N7 serves as a second node D2 of the lower branch chargepump 124. In this embodiment, the first node D1 of the lower branchcharge pump 124 connect to the front boosting stage 120_1 via the inputpad IN2. The second node D2 of the lower branch charge pump 124 connectto the rear boosting stage 1203 via the output pad OUT2. The sourceterminal and the drain terminal of the pre-charge transistor N10 arerespectively coupled to the gate terminal of the main transistor N7 andthe first node D1 of the lower branch charge pump 124, and the gateterminal of the pre-charge transistor N10 is coupled to the second nodeD2 of the lower branch charge pump 124. The body of the pre-chargetransistor N10 are connected to the body BD of the main pass transistorN7. One terminal of the capacitor C4 is coupled to the gate terminal ofthe main pass transistor N7, and the other terminal of the capacitor C4receives the clock signal P44. One terminal of the capacitor C3 iscoupled to the second node D2 of the lower branch charge pump 124, andthe other terminal of the capacitor C3 receives the clock signal P11.The source terminals and the bodies of the two substrate transistors N8and N9 are connected together to the body BD of the main pass transistorN7, and the drain terminals of the two substrate transistors N8 and N9are connected respectively to the first node D1 and the second node D2of the lower branch charge pump 124. The gate terminal of the substratetransistor N9 is connected to the first node D1 of the lower branchcharge pump 124, and the gate terminal of the substrate transistor N8 isconnected to the first node U1 of the upper branch charge pump 122. Thatis to say, in the lower branch charge pump 124 of the presentembodiment, the gate terminal of one substrate transistor N9, whosedrain terminal connects to the second node D2, is connected to the firstnode D1 of one branch charge pump 124 that the one substrate transistorN9 is located, and the gate terminal of the other substrate transistorN8 is connected to the first node U1 of the other branch charge pump122. The substrate transistors N8 and N9 are switched to keep potentialat the body BD of the main pass transistor N7 at a lower substrate levelto mitigate the body effect. The drain terminal and the source terminalof the initial transistor N13 are respectively coupled to the first nodeand the second node of the lower branch charge pump 124, i.e., the inputpad IN2 and the output pad OUT2. The gate terminal of the initialtransistor N13 is coupled to the drain terminal itself, and the body ofthe initial transistor N13 are connected to the body BD of the main passtransistor N7.

In the embodiments as exemplarily disclosed in FIG. 1, FIG. 3 and FIG.4, the main pass transistors NO and N7, the pre-charge transistors N3and N10, the substrate transistors N1, N2, N8 and N9 and the initialtransistors N6 and N13 of the boosting stages 120_1 to 120_N areN-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

FIG. 5 illustrates an internal circuit structure of the output stageaccording to the embodiment of FIG. 1.

In the present embodiment, the output stage 110 includes an upper branchoutput circuit 111 and a lower branch output circuit 113. The upperbranch output circuit 111 includes a main pass transistor NO, apre-charge transistor N3, one capacitor C2, two substrate transistors N1and N2. The source terminal of the main pass transistor NO serves as afirst node UN of the upper branch output circuit 111, and the drainterminal of the main pass transistor NO serves as a second node U(N+1)of the upper branch output circuit 111. In this embodiment, the firstnode UN of the upper branch output circuit 111 connect to the frontboosting stage 120_N via the input pad IN1. The second node U(N+1) ofthe upper branch output circuit 111 outputs the boosted voltage VPP viaan output pad OUT. The source terminal and the drain terminal of thepre-charge transistor N3 are respectively coupled to the gate terminalof the main transistor NO and the first node UN of the upper branchoutput circuit 111, and the gate terminal of the pre-charge transistorN3 is coupled to the second node U(N+1) of the upper branch outputcircuit 111. The body of the pre-charge transistor N3 are connected tothe body BU of the main pass transistor NO. One terminal of thecapacitor C2 is coupled to the gate terminal of the main pass transistorN0, and the other terminal of the capacitor C2 receives the clock signalP44. The source terminals and the bodies of the two substratetransistors N1 and N2 are connected together to the body BU of the mainpass transistor NO, and the drain terminals of the two substratetransistors N1 and N2 are connected respectively to the first node UNand the second node U(N+1) of the upper branch output circuit 111. Thegate terminal of the substrate transistor N2 is connected to the firstnode UN of the upper branch output circuit 111, and the gate terminal ofthe substrate transistor N1 is connected to the first node DN of thelower branch output circuit 113. That is to say, in the upper branchoutput circuit 111 of the present embodiment, the gate terminal of onesubstrate transistor N2, whose drain terminal connects to the secondnode U(N+1), is connected to the first node UN of one branch outputcircuit 111 that the one substrate transistor N2 is located, and thegate terminal of the other substrate transistor N1 is connected to thefirst node DN of the other branch output circuit 113. The substratetransistors N1 and N2 are switched to keep potential at the body BU ofthe main pass transistor NO at a lower substrate level to mitigate thebody effect.

Similarly, the lower branch output circuit 113 also includes a main passtransistor N7, a pre-charge transistor N10, one capacitor C4, twosubstrate transistors N8 and N9 and an initial transistor N13. Thesource terminal of the main pass transistor N7 serves as a first node DNof the lower branch output circuit 113, and the drain terminal of themain pass transistor N7 serves as a second node D(N+1) of the lowerbranch output circuit 113. In this embodiment, the first node DN of thelower branch output circuit 113 connect to the front boosting stage120_N via the input pad IN2. The second node D(N+1) of the lower branchoutput circuit 113 outputs the boosted voltage VPP via the same outputpad as that of the upper branch output circuit 111. The source terminaland the drain terminal of the pre-charge transistor N10 are respectivelycoupled to the gate terminal of the main transistor N7 and the firstnode DN of the lower branch output circuit 113, and the gate terminal ofthe pre-charge transistor N10 is coupled to the second node D(N+1) ofthe lower branch output circuit 113. The body of the pre-chargetransistor N10 are connected to the body BD of the main pass transistorN7. One terminal of the capacitor C4 is coupled to the gate terminal ofthe main pass transistor N7, and the other terminal of the capacitor C4receives the clock signal P22. The source terminals and the bodies ofthe two substrate transistors N8 and N9 are connected together to thebody BD of the main pass transistor N7, and the drain terminals of thetwo substrate transistors N8 and N9 are connected respectively to thefirst node DN and the second node D(N+1) of the lower branch outputcircuit 113. The gate terminal of the substrate transistor N9 isconnected to the first node DN of the lower branch output circuit 113,and the gate terminal of the substrate transistor N8 is connected to thefirst node UN of the upper branch output circuit 111. That is to say, inthe lower branch output circuit 113 of the present embodiment, the gateterminal of one substrate transistor N9, whose drain terminal connectsto the second node D(N+1), is connected to the first node DN of onebranch output circuit 113 that the one substrate transistor N9 islocated, and the gate terminal of the other substrate transistor N8 isconnected to the first node UN of the other branch output circuit 111.The substrate transistors N8 and N9 are switched to keep potential atthe body BD of the main pass transistor N7 at a lower substrate level tomitigate the body effect.

In the embodiment as exemplarily disclosed in FIG. 5, the main passtransistors NO and N7, the pre-charge transistors N3 and N10 and thesubstrate transistors N1, N2, N8 and N9 of the output stage 110 areN-channel MOSFETs. The boosted voltage VPP is a positive voltage, andthereby the four-phase charge pump circuit 100 is a positive charge pumpcircuit.

With reference to FIG. 2A to FIG. 4, the upper branch charge pumps 121and 122 and the lower branch charge pumps 123 and 124 are driven by thefour clock signals P11, P22, P33 and P44 as shown in FIG. 2A, so as toperform a voltage boosting operation stage by stage. The main passtransistors NO and N7 in accompaniment with the substrate transistorsN1, N2, N8 and N9 perform a bias switching operation to keep the bias ofthe main pass transistors NO and N7 at a lower substrate level thusmitigating the body effect.

FIG. 2A shows waveforms of four-phase clock signals applied for thecircuit of FIG. 1 in accordance with an embodiment of the disclosure. Inthe following description, the operation of the first boosting stage120_1 is divided into several time periods P1 to P3. The operations ofthe boosting stages 120_3 . . . and 120_(N−1) (not shown in FIG. 1) canbe deduced by analogy.

Referring to FIG. 2A to FIG. 3, during the first time period P1, theclock signals P33 and P44 are at high levels, and the clock signals P11and P22 are at low levels. In the upper branch charge pump 121, the mainpass transistors NO is turned on, and the input voltage VDD istransmitted from the first node U0 to the second node U1. In the lowerbranch charge pump 123, the pre-charge transistor N10 is turned on topre-charge the gate terminal GD0 of the main pass transistors N7 byusing the input voltage VDD and reduce the reverse current of the mainpass transistors N7. For mitigating the body effect, the substratetransistors N2 and N8 are turned on by the input voltage VDD, so thatpotential at the body BU of the main pass transistor NO and the body BDof the main pass transistor N7 is kept at a lower substrate level duringthe first time period P1. For the potential at the body BU of the mainpass transistor NO, the lower substrate level may be the voltage levelVIN1-Vth or VOUT1-Vth, where VIN1 and VOUT1 are voltages at the firstnode U0 and the second node U1 respectively, and Vth is a thresholdvoltage of the substrate transistor N1 or N2. For the potential at thebody BU of the main pass transistor N7, the lower substrate level may bethe voltage level VIN2-Vth or VOUT2-Vth, where VIN2 and VOUT2 arevoltages at the first node D0 and the second node D1 respectively, andVth is a threshold voltage of the substrate transistor N8 or N9. In thisembodiment, there is no front boosting stage disposed prior to the firstboosting stage 120_1, the substrate transistors N2 and N8 may be turnedon by the input voltage VDD during the first time period P1. Theoperations of the boosting stages 120_3 . . . and 120_(N−1) (not shownin FIG. 1) during the first time P1 can be deduced by analogy. However,for the boosting stage 120_3, the substrate transistors N2 and N8 may beturned on by the clock signal P33 of the front boosting stage 120_2during the first time period P1, for example.

During the second time period P2, the clock signal P33 and P44 changefrom the high levels to the low levels, and the clock signals P11 andP22 change from the low levels to the high levels. In the upper branchcharge pump 121, the main pass transistors NO is turned off, and thepre-charge transistor N3 is turned on. The voltage VDD at the secondnode U1 is boosted to a middle boosted voltage 2VDD, and then the middleboosted voltage 2VDD is outputted to the rear boosting stage, e.g., theboosting stage 120_2, via the output pad OUT1. In the lower branchcharge pump 123, the pre-charge transistor N10 is turned off, and themain pass transistors N7 is turned on. The input voltage VDD at thefirst node D0 is transmitted to the node D1. The transmitted voltage VDDat the second node D1 may change to the middle boosted voltage VDD dueto the low level of the clock signal P33, and then the middle boostedvoltage VDD is outputted to the rear boosting stage via the output padOUT2. For mitigating the body effect, the substrate transistors N1 andN9 are turned on by the clock signal P11 of the front boosting stage, sothat potential at the body BU of the main pass transistor N0 and thebody BD of the main pass transistor N7 is kept at the lower substratelevel during the second time period P2. In this embodiment, there is nofront boosting stage disposed prior to the first boosting stage 120_1,the substrate transistors N1 and N9 may be turned on by the inputvoltage VDD during the second time period P2. For the boosting stage120_3, the substrate transistors N1 and N9 may be turned on by the clocksignal P11 of the front boosting stage 120_2 during the second timeperiod P2, for example.

During the third time period P3, the clock signals P33 and P44 changefrom the low levels to the high levels, and the clock signals P11 andP22 change from the high levels to the low levels. For the upper branchcharge pumps 121 and 122, the middle boosted voltage 2VDD at the secondnode U1 of the upper branch charge pump 121 and the middle boostedvoltage 2VDD transmitted to the first node U1 of the upper branch chargepump 122 via the output pad OUT1 may change to the voltage VDD due tothe low level of the clock signal P11. For the lower branch charge pumps123 and 124, the voltage VDD at the second node D1 of the lower branchcharge pump 123 and the voltage VDD transmitted to the first node D1 ofthe lower branch charge pump 124 via the output pad OUT2 may change tothe voltage 2VDD due to the high level of the clock signal P33.

In the present embodiment, since the bodies of the pre-chargetransistors N3 and N10, the substrate transistors N1, N2, N8 and N9 andthe initial transistors N6 and N13 are correspondingly connected to thebody BU of the main pass transistor NO and the body BD of the main passtransistor N7, potential at the bodies of the pre-charge transistors N3and N10, the substrate transistors N1, N2, N8 and N9 and the initialtransistors N6 and N13 is also kept at the lower substrate level duringthe first time period P1 and the second time period P2, and thus thebody effect is mitigated.

In the following description, the operation of the second boosting stage120_2 is divided into several time periods P2 to P3. The operations ofthe boosting stages 120_4 (not shown in FIG. 1) . . . and 120_N can bededuced by analogy.

Referring to FIG. 2A to FIG. 4, during the second time period P2, theclock signals P11 and P22 are at high levels, and the clock signals P33and P44 are at low levels. In the upper branch charge pump 122, the mainpass transistors NO is turned on, and the middle boosted voltage 2VDDreceived from the upper branch charge pump 121 of the boosting stage120_1 is transmitted from the first node U1 to the second node U2. Inthe lower branch charge pump 124, the pre-charge transistor N10 isturned on to pre-charge the gate terminal GD0 of the main passtransistors N7 by using the middle boosted voltage VDD received from thelower branch charge pump 123 of the boosting stage 120_1, and reduce thereverse current of the main pass transistors N7. For mitigating the bodyeffect, the substrate transistors N2 and N8 are turned on by the clocksignal P11 of the front boosting stage, so that potential at the body BUof the main pass transistor NO and the body BD of the main passtransistor N7 is kept at a lower substrate level during the second timeperiod P2. For the potential at the body BU of the main pass transistorNO, the lower substrate level may be the voltage level VIN1-Vth orVOUT1-Vth, where VIN1 and VOUT1 are voltages at the first node U1 andthe second node U2 respectively, and Vth is a threshold voltage of thesubstrate transistor N1 or N2. For the potential at the body BU of themain pass transistor N7, the lower substrate level may be the voltagelevel VIN2-Vth or VOUT2-Vth, where VIN2 and VOUT2 are voltages at thefirst node D1 and the second node D2 respectively, and Vth is athreshold voltage of the substrate transistor N8 or N9.

During the third time period P3, the clock signals P33 and P44 changefrom the low levels to the high levels, and the clock signals P11 andP22 change from the high levels to the low levels. In the upper branchcharge pump 122, the main pass transistors NO is turned off, and thepre-charge transistor N3 is turned on. The middle boosted voltage 2VDDat the second node U2 is boosted to a middle boosted voltage 3VDD, andthen the middle boosted voltage 3VDD at the second node U2 is outputtedto the rear boosting stage, e.g., the boosting stage 120_3, via theoutput pad OUT1. In the lower branch charge pump 124, the pre-chargetransistor N10 is turned off, and the main pass transistors N7 is turnedon. The middle boosted voltage VDD at the first node D1 is boosted to amiddle boosted voltage 2VDD, and the middle boosted voltage 2VDDtransmitted from the first node D1 to the second node D2. The middleboosted voltage 2VDD at the second node D2 may change to the middleboosted voltage 3VDD due to the high level of the clock signal P11during the second time period P2, and then may change to the middleboosted voltage 2VDD due to the low level of the clock signal P33 duringthe third time period P3. The middle boosted voltage 2VDD at the secondnode D2 is outputted to the rear boosting stage via the output pad OUT2.For mitigating the body effect, the substrate transistors N1 and N9 areturned on by the clock signal P33 of the front boosting stage, so thatpotential at the body BU of the main pass transistor NO and the body BDof the main pass transistor N7 is kept at the lower substrate levelduring the third time period P3.

In the present embodiment, since the bodies of the pre-chargetransistors N3 and N10, the substrate transistors N1, N2, N8 and N9 andthe initial transistors N6 and N13 are correspondingly connected to thebody BU of the main pass transistor NO and the body BD of the main passtransistor N7, potential at the bodies of the pre-charge transistors N3and N10, the substrate transistors N1, N2, N8 and N9 and the initialtransistors N6 and N13 is also kept at the low level during the secondtime period P2 and the third time period P3, and thus the body effect ismitigated.

In the embodiment as exemplarily disclosed in FIG. 3 and FIG. 4, theinitial transistors N6 and N13 serve as starters and are configured torespectively provide an initial potential at the second nodes U1 and D1to start up waveforms of the boosted voltages outputted via the outputpads OUT1 and OUT2. In the disclosure, the boosting stages may havedifferent circuit structures in response to an actual designrequirement, and the initial transistors N6 and N13 may be omitted inother exemplary embodiments.

In the following description, the operation of the output stage 110 isdivided into several time periods P2 to P3. Referring to FIG. 2A to FIG.5, during the second time period P2, the clock signal P22 is at the highlevel, and the clock signal P44 is at the low level. In the lower branchoutput circuit 113, the main pass transistors N7 is turned on, and themiddle boosted voltage (N+1)VDD received from the lower branch chargepump 124 of the boosting stage 120_N is transmitted from the first nodeDN to the second node D(N+1), where the middle boosted voltage (N+1)VDDis (N+1) times larger than the input voltage VDD. In the upper branchoutput circuit 111, the pre-charge transistor N3 is turned on topre-charge the gate terminal GU0 of the main pass transistors NO andreduce the reverse current of the main pass transistors N0. Formitigating the body effect, the substrate transistors N1 and N9 areturned on by the clock signal P11 of the front boosting stage, e.g., thelast boosting stage 120_N, so that potential at the body BU of the mainpass transistor NO and the body BD of the main pass transistor N7 iskept at a lower substrate level during the second time period P2. Forthe potential at the body BU of the main pass transistor NO, the lowersubstrate level may be the voltage level VIN1-Vth or VOUT-Vth, whereVIN1 and VOUT are voltages at the first node UN and the second nodeU(N+1) respectively, and Vth is a threshold voltage of the substratetransistor N1 or N2. For the potential at the body BU of the main passtransistor N7, the lower substrate level may be the voltage levelVIN2-Vth or VOUT-Vth, where VIN2 and VOUT are voltages at the first nodeDN and the second node D(N+1) respectively, and Vth is a thresholdvoltage of the substrate transistor N8 or N9.

During the third time period P3, the clock signal P44 changes from thelow level to the high level, and the clock signal P22 changes from thehigh level to the low level. In the lower branch output circuit 113, themain pass transistors N7 is turned off, and the pre-charge transistorN10 is turned on. In the upper branch output circuit 111, the pre-chargetransistor N3 is turned off, and the main pass transistors NO is turnedon. The middle boosted voltage (N+1)VDD received from the upper branchcharge pump 122 of the boosting stage 120_N is transmitted from thefirst node UN to the second node U(N+1), where the middle boostedvoltage (N+1)VDD is N+1 times larger than the input voltage VDD. Themiddle boosted voltage (N+1)VDD at the second node U(N+1) is outputtedvia the output pad of the output stage 110 to serve as the boostedvoltage VPP. For mitigating the body effect, the substrate transistorsN2 and N8 are turned on by the clock signal P33 of the front boostingstage, e.g., the last boosting stage 120_N, so that potential at thebody BU of the main pass transistor NO and the body BD of the main passtransistor N7 is kept at the low level during the third time period P3.

In the present embodiment, since the bodies of the pre-chargetransistors N3 and N10 and the substrate transistors N1, N2, N8 and N9are correspondingly connected to the body BU of the main pass transistorNO and the body BD of the main pass transistor N7, potential at thebodies of the pre-charge transistors N3 and N10 and the substratetransistors N1, N2, N8 and N9 is also kept at the lower substrate levelduring the second time period P2 and the third time period P3, and thusthe body effect is mitigated.

FIG. 2B shows waveforms of four-phase clock signals applied for thecircuit of FIG. 1 in accordance with another embodiment of thedisclosure. With reference to FIG. 1 and FIG. 2B, the waveforms of thefour-phase clock signals P11′, P22′, P33′ and P44′ of this embodimentare similar to that the waveforms of the four-phase clock signals P11,P22, P33 and P44 as shown in FIG. 2A. The main difference therebetween,for example, lies in that during the transition state Ptr12, the fallingedge of the clock signal P33′ leads before the rising edge of the clocksignal P11′, and during the transition state Ptr23, the falling edge ofthe clock signal P11′ leads before the rising edge of the clock signalP33′ as shown in FIG. 2B. In the exemplary embodiment, each of themultiple boosting stages 120_1 to 120_N may also be driven by thefour-phase clock signals P11′, P22′, P33′ and P44′. The output stage 110may also be driven by the four-phase clock signals P22′ and P44′.

Besides, the operation of the four-phase charge pump circuit driven bythe four-phase clock signals P11′, P22′, P33′ and P44′ described in thisembodiment of the disclosure is sufficiently taught, suggested, andembodied in the exemplary embodiments illustrated in FIG. 1 to FIG. 5,and therefore no further description is provided herein.

FIG. 6 illustrates a schematic structure drawing of the multipleboosting stages according to an exemplary embodiment of the disclosure.Referring to FIG. 6, a deep doped region 620 is disposed on a p-typesubstrate 610. The deep doped region 620 may be manufactured as a deepN-well or an N+ buried layer according to different semiconductorprocesses. The deep doped region 620 is biased at a maximum voltage ofthe system that that four-phase charge pump circuit 100 is located orthe positive boosted voltage VPP in this embodiment. On the deep dopedregion 620, the boosting stages 120_1 to 120_N are processed incorresponding P-wells. N-wells are respectively disposed between theP-wells for spacing the boosting stages 120_1 to 120_N. In the presentembodiment, the main pass transistors NO and N7, the pre-chargetransistors N3 and N10, the substrate transistors N1, N2, N8 and N9 andthe initial transistors N6 and N13 of the boosting stages 120_1 to 120_Nare disposed on the identical deep doped region 620. That is to say,NMOS type charge pumps simply use a single deep N-well, and the occupiedchip area of the NMOS type charge pumps is smaller than that of the PMOStype charge pumps.

In the present embodiment, the main pass transistors NO and N7, thepre-charge transistors N3 and N10 and the substrate transistors N1, N2,N8 and N9 of the output stage 110 may also be disposed on the identicaldeep doped region 620, and the disclosure is not limited thereto.

FIG. 7 illustrates a schematic circuit diagram of each transistor of theboosting stages. Referring to FIG. 6 and FIG. 7, since the main passtransistors NO and N7, the pre-charge transistors N3 and N10, thesubstrate transistors N1, N2, N8 and N9 and the initial transistors N6and N13 of the boosting stages 120_1 to 120_N are N-channel MOSFETs anddisposed on the identical deep doped region 620, each of the main passtransistors NO and N7, the pre-charge transistors N3 and N10, thesubstrate transistors N1, N2, N8 and N9 and the initial transistors N6and N13 of the boosting stages 120_1 to 120_N may be expressed with thecircuit diagram as illustrated in FIG. 7 to show that the transistorsare disposed on the same deep doped region.

FIG. 8 is a schematic diagram of a four-phase charge pump circuitaccording to another embodiment of the disclosure. Referring to FIG. 1and FIG. 8, the four-phase charge pump circuit 800 of the presentembodiment is similar to the four-phase charge pump circuit 100 of theembodiment of FIG. 1, and a main difference there between is that thefour-phase charge pump circuit 800 further includes an output stage 830.The output stage 830 may be coupled to a boosting stage 820_1 (not shownin FIG. 8) and extract a middle boosted voltage from the boosting stage820_I in the present embodiment, where I is a positive integer, and2≦I≦N. The output stage 830 enhances the capability of the extractedmiddle boosted voltage, so as to output another boosted voltage VPP2 viaan output pad OUTB. It should be noticed that the number of the boostingstages and the number of the output stages of the present embodiment arenot limited by the disclosure.

Besides, the operation of the four-phase charge pump circuit describedin this embodiment of the disclosure is sufficiently taught, suggested,and embodied in the exemplary embodiments illustrated in FIG. 1 to FIG.7, and therefore no further description is provided herein.

In summary, in the exemplary embodiments of the disclosure, thetransistors of the multiple boosting stages are N-channel MOSFETs anddisposed on the same deep doped region, and thereby the occupied chiparea may be reduced and smaller than that of the charge pump circuitwhose deep doped region are separated for each boosting stage. In theexemplary embodiments of the disclosure, the substrate transistors areswitched to keep potential at the bodies of the main pass transistors atthe low level to mitigate the body effect. The pre-charge transistorsmay pre-charge gate voltages of the main pass transistors and reducereverse currents thereof. Moreover, the initial transistors may providethe initial potential to start up waveforms of the boosted voltages.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of thedisclosure without departing from the scope or spirit of the disclosure.In view of the foregoing, it is intended that the disclosure covermodifications and variations of this disclosure provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A four-phase charge pump circuit comprising:multiple boosting stages driven by four-phase clock signals, whereineach of the boosting stages comprises two branch charge pumps, and eachof the two branch charge pumps comprises: a main pass transistor havinga body, a gate terminal, a source terminal as a first node of the branchcharge pump and a drain terminal as a second node of the branch chargepump, wherein the first node and the second node of the branch chargepump connect respectively to a front boosting stage and a rear boostingstage of the boosting stages; and a pre-charge transistor having a gateterminal, a source terminal and a drain terminal, wherein the sourceterminal and the drain terminal of the pre-charge transistor arerespectively coupled to the gate terminal of the main transistor and thefirst node of the branch charge pump, and the gate terminal of thepre-charge transistor is coupled to the second node of the branch chargepump, wherein the main pass transistors and the pre-charge transistorsof the boosting stages are disposed on an identical deep doped region.2. The four-phase charge pump circuit as claimed in claim 1, whereineach of the two branch charge pumps further comprises: two capacitorscoupled respectively to the gate terminal of the main pass transistorand the second node of the branch charge pump.
 3. The four-phase chargepump circuit as claimed in claim 2, wherein for each of the boostingstages, the two capacitors of one branch charge pump receive two clocksignals of the four-phase clock signals, and the two capacitors of theother branch charge pump receive the other two clock signals of thefour-phase clock signals.
 4. The four-phase charge pump circuit asclaimed in claim 1, wherein each of the two branch charge pumps furthercomprises: two substrate transistors, each of the two substratetransistors having a body, a gate terminal, a source terminal and adrain terminal, wherein the source terminals and the bodies of the twosubstrate transistors are connected together to the body of the mainpass transistor, and the drain terminals of the two substratetransistors are connected respectively to the first node and the secondnode of the branch charge pump, wherein the gate terminal of onesubstrate transistor, whose drain terminal connects to the second node,is connected to the first node of one branch charge pump that the onesubstrate transistor is located, and the gate terminal of the othersubstrate transistor is connected to the first node of the other branchcharge pump.
 5. The four-phase charge pump circuit as claimed in claim4, wherein each of the two branch charge pumps further comprises: aninitial transistor having a body, a gate terminal, a source terminal anda drain terminal, wherein the drain terminal and the source terminal ofthe initial transistor are respectively coupled to the first node andthe second node of the branch charge pump, the gate terminal of theinitial transistor is coupled to the drain terminal of the initialtransistor, and the body of the initial transistor are connected to thebody of the main pass transistor.
 6. The four-phase charge pump circuitas claimed in claim 5, wherein potential at the body of each of the mainpass transistors and the initial transistors of the boosting stages iskept at a lower substrate level.
 7. The four-phase charge pump circuitas claimed in claim 5, wherein the substrate transistors and the initialtransistors of the boosting stages are disposed on the identical deepdoped region.
 8. The four-phase charge pump circuit as claimed in claim5, wherein the main pass transistors, the pre-charge transistors, thesubstrate transistors and the initial transistors of the boosting stagesare N-channel metal-oxide-semiconductor field-effect transistors(MOSFETs).
 9. The four-phase charge pump circuit as claimed in claim 1further comprising: an output stage driven by two clock signals of thefour-phase clock signals and outputting a boosted voltage, wherein themultiple boosting stages are coupled to the output stage.
 10. Thefour-phase charge pump circuit as claimed in claim 9, wherein the outputstage comprises two branch output circuits, and each of the two branchoutput circuits comprises: a main pass transistor having a body, a gateterminal, a source terminal as a first node of the branch output circuitand a drain terminal as a second node of the branch output circuit,wherein the first node of the branch output circuit connects to a frontboosting stage of the boosting stages, and the second node of the branchoutput circuit serves as an output end of the output stage to output theboosted voltage; and a pre-charge transistor having a gate terminal, asource terminal and a drain terminal, wherein the source terminal andthe drain terminal of the pre-charge transistor are respectively coupledto the gate terminal of the main transistor and the first node of thebranch output circuit, and the gate terminal of the pre-chargetransistor is coupled to the second node of the branch output circuit,wherein the main pass transistors and the pre-charge transistors of theoutput stage are disposed on the identical deep doped region.
 11. Thefour-phase charge pump circuit as claimed in claim 10, wherein each ofthe two branch output circuits further comprises: one capacitor coupledto the gate terminal of the main pass transistor, wherein the capacitorsof the output stage receive two clock signals of the four-phase clocksignals.
 12. The four-phase charge pump circuit as claimed in claim 10,wherein each of the two branch charge pumps further comprises: twosubstrate transistors, each having a body, a gate terminal, a sourceterminal and a drain terminal, wherein the source terminals and thebodies of the two substrate transistors are connected together to thebody of the main pass transistor, and the drain terminals of the twosubstrate transistors are connected respectively to the first node andthe second node of the branch output circuit, wherein the gate terminalof one substrate transistor, whose drain terminal connects to the secondnode, is connected to the first node of one branch output circuit thatthe one substrate transistor is located, and the gate terminal of theother substrate transistor is connected to the first node of the otherbranch output circuit.
 13. The four-phase charge pump circuit as claimedin claim 12, wherein potential at the body of each of the main passtransistors of the output stage is kept at a lower substrate level. 14.The four-phase charge pump circuit as claimed in claim 12, wherein thesubstrate transistors of the output stage are disposed on the identicaldeep doped region.
 15. The four-phase charge pump circuit as claimed inclaim 12, wherein the main pass transistors, the pre-charge transistorsand the substrate transistors of the output stage are N-channel MOSFETs.16. The four-phase charge pump circuit as claimed in claim 1, whereinthe four-phase charge pump circuit is a positive charge pump circuit.